Embodiments of the present invention relate to a serial communication test device, a system including the same, and a method thereof, and more particularly to a technology that allows a master chip and a slave ship for Serial Peripheral Interface (SPI) communication to check data, resulting in increased reliability.
Generally, a Serial Peripheral Interface (SPI) device is installed in a master chip (e.g., CPU), for the SPI device to perform data communication between the master chip and the slave chip (e.g., a peripheral device such as a multimedia device). The SPI device is configured to use a serial communication scheme. Unlike other serial communication schemes, the SPI device enables the master chip and the slave chip to simultaneously communicate with each other using clock synchronization. In other words, the SPI device enables the CPU and the peripheral device to simultaneously communicate with each other to communicate valid data simultaneously between the CPU and the peripheral device.
Further, the SPI device, serving as an interface configured to implement serial communication between two devices, is configured to use a data output pin, a data input pin, a clock pin, and a slave selection pin thereof. Accordingly, the SPI device operates as a simple and serial interface and at the same time operates at a high speed, so that convenient and various functions can be implemented. In addition, the SPI device is a protocol that adds or connects various peripheral devices to applications having rapidly changing large capacity data, such as a video game system, a digital camera, a car audio, a navigation system, a set-top box, a PDA, an MP3 player, etc.
Moreover, the SPI device is accommodated into communication systems configured to perform communication between a central processing unit (CPU) and one or more peripheral devices. However, the SPI device is configured to interconnect two microprocessors to allow the two microprocessors to communicate with each other. One microprocessor may operate in a master mode, and the other microprocessor may operate in a slave mode. On the contrary, a conventional SPI device may be unable to determine whether data has been correctly transferred from the master chip to the slave chip using the master chip or the slave chip. In other words, when an unexpected error occurs in transmission/reception (Tx/Rx) data, the conventional SPI device may have difficulty in recognizing whether the error occurs by malfunction of the master chip used for data transmission, whether the master chip initially transmits erroneous data, whether the error occurs in communication between the master chip and the slave chip, or whether the error occurs due to a malfunction of the slave chip receiving data. As a result, the master chip and the slave chip may be unable to recognize the presence or absence of error(s) in data communication, resulting in a potential malfunction.
To improve a serial communication quality, the SPI device may perform error detection and error correction. The master chip should detect errors of read data as well as obtain either parity information requisite for error correction or Cyclic Redundancy Check (CRC) information. However, the conventional error check scheme uses a significantly long time period for error detection or error correction, and is unable to correctly perform error checking.